1. Field of the Invention
The present invention relates to structures of a voltage generating circuit for generating a voltage required stably with low power consumption, and more particularly, to a structure implementing, in use in a semiconductor memory device, low power consumption and low voltage operation of the semiconductor memory device.
2. Description of the Background Art
A dynamic random access memory (DRAM) has found expanded application to portable appliances such as a notebook personal computer. Such a portable appliance uses a battery as its power source. Each component must operate with as low power consumption as possible in order to make the battery life as long as possible. In the DRAM, an external power supply voltage of 5 V, for example, is internally down-converted to 3.3 V for example, and the internally down-converted voltage is used as operation power supply voltage, in order to implement low power consumption. The low power supply voltage decreases the amplitude of a signal, thereby reducing current consumption associated with charge/discharge of a signal line.
FIG. 54 is a diagram showing the entire structure of a conventional DRAM. Referring to FIG. 54, the conventional DRAM includes a memory cell array 1 having memory cells MC arranged in a matrix of rows and columns. Memory cell array 1 is divided into two array blocks MAR and MAL. Array blocks MAR and MAL each include a plurality of word lines arranged corresponding to each row of memory cells, and a plurality of bit line pairs arranged corresponding to each column of memory cells.
In FIG. 54, for simplicity of illustration, memory cells MC1 and MC2 in array blocks MAL and MAR are representatively shown. Memory cell MC1 included in array block MAL is arranged corresponding to a crossing portion of a word line WLL and a bit line BLL, and includes a capacitor 12 for storing information, and an access transistor 13 formed of an n channel MOS transistor rendered conductive in response to a signal potential on word line WLL for connecting capacitor 12 to bit line BLL. An intermediate voltage VH from a Vcc/2 generating circuit 2 to be described later is applied to the electrode (cell plate) of capacitor 12.
Memory cell MC2 included in array block MAR is arranged corresponding to a crossing portion of a word line WLR and a bit line BLR, and includes a capacitor 14 and an access transistor 15 formed of an n channel MOS transistor rendered conductive in response to a signal potential on word line WLR for connecting capacitor 14 to bit line BLR. Intermediate voltage VH from Vcc/2 generating circuit 2 is applied to the cell plate of capacitor 14. Bit line BLL is paired with a bit line /BLL, and bit line BLR is paired with a bit line /BLR. In a respective bit line pair, data of a memory cell is transmitted to one bit line, and the other bit line provides a comparison reference voltage of the memory cell data.
Between a bit line pair BLL, /BLL and a bit line pair BLR, /BLR, provided are a sense amplifier 21 activated in response to a sense amplifier drive signal .phi.p for differentially amplifying potentials on a selected bit line pair, block select gates 22 and 23 rendered conductive in response to an array block select signal .PHI.R from a signal .PHI. generating circuit 10 for connecting bit lines BLR and/BLR to sense amplifier 21, block select gates 16 and 17 rendered conductive in response to an array block select signal .PHI.L from signal .PHI. generating circuit 10 for connecting bit lines BLL and /BLL to sense amplifier 21, and transistors 18, 19, and 20 precharging and equalizing potentials on bit lines BLL, /BLL, BLR, and /BLR to intermediate voltage VH in response to a bit line equalize signal BLEQ from a BLEQ generating circuit 9.
Transistors 18 and 19 transmit intermediate voltage VH to bit lines BLL and BLR, and bit lines /BLL and /BLR, respectively, in response to bit line equalize signal BLEQ. Transistor 20 electrically connects bit lines BLL and BLR, and bit lines /BLL and /BLR, in response to bit line equalize signal BLEQ.
The conventional DRAM further includes an internal Vcc generating circuit 4 down-converting an external power supply voltage EXV and generating an internal power supply voltage Vcc1, a Vpp generating circuit 5 generating an internal high voltage Vpp higher than internal power supply voltage vcc1 from internal power supply voltage Vcc1, and a sense amplifier drive signal generating circuit 6 generating sense amplifier drive signal .phi.p at the internal power supply voltage Vcc1 level at a prescribed timing in response to a timing signal (signal path of which is not shown) from a control circuit 7 to be described later.
Control circuit 7 receives an address signal Add, a row address strobe signal /RAS, a column address strobe signal /CAS, an output enable signal /OE, and a write enable signal /WE, and generates an internal address signal (not shown) and a control signal determining an operation timing of each internal circuit. Control circuit 7 further generates internal write data from external write data Din, and external read data Dout from internal read data.
The conventional DRAM further includes a word line decoder 8 provided corresponding to array block MAL for decoding an internal address signal from control circuit 7 and transmitting a word line drive signal at the internal high voltage level from Vpp generating circuit 5 onto a corresponding word line of array block MAL, and a word line decoder 11 provided corresponding to array block MAR for decoding an internal address signal from control circuit 7 and transmitting a word line drive signal at the internal high voltage Vpp level from Vpp generating circuit 5 onto a selected word line (word line corresponding to an addressed row).
BLEQ generating circuit 9 generates bit line equalize signal BLEQ at the internal power supply voltage Vcc1 level in response to an internal control signal from control circuit 7. Signal .PHI. generating circuit 10 brings one of block select signals .PHI.L and .PHI.R to a non-active state according to part of an internal control signal and an internal address signal from control circuit 7. Note that, in the following description, "generating a signal" means "bringing a signal to an active state". More specifically, signal .PHI. generating circuit 10 connects an array block including a selected word line to sense amplifier 21, and disconnects a non-selected array block from sense amplifier 21. At the time of stand-by, signals .PHI.L and .PHI.R are in an active state of "H", block select gates 16, 17, 22 and 23 are all turned on, and bit lines BLL, /BLL, BLR, /BLR are all precharged to intermediate voltage VH.
Vpp generating circuit 5 generates a negative voltage Vbb at a prescribed voltage level from internal power supply voltage Vcc1, and applies negative voltage Vpp to a region of a semiconductor substrate on which memory cell array 1 is formed. The negative voltage Vbb prevents generation of a parasitic MOS transistor (insulated gate type field effect transistor), reduces parasitic capacitance caused by a PN junction between the substrate and an impurity region, and stabilizes the threshold voltage of an access transistor. Data writing/reading operation will now be described briefly.
At the time of stand-by, row address strobe signal /RAS is in a non-active state at an "H" level. In this state, word lines WLL and WLR are both at an "L" level, and access transistors 13 and 15 are both in an off state. Bit line equalize signal BLEQ is at "H" at the internal power supply voltage Vcc1 level, transistors 18, 19, and 20 are in an on state, and bit lines BLL, /BLL, BLR, and /BLR are precharged and equalized to intermediate voltage VH (block select gates 16, 17, 22 and 23 are in an on state).
In response to the falling of signal /RAS to the "L" level, a memory cycle starts. In this state, bit line equalize signal BLEQ from BLEQ generating circuit 9 attains the "L" level, and transistors 18, 19 and 20 are turned off. Accordingly, bit lines BLL, /BLL, BLR, and /BLR are brought to a floating state of intermediate voltage VH. In response to the falling of signal /RAS, external address signal Add is strobed, and an internal address signal is provided from control circuit 7. The internal address signal includes a block address designating an array block. According to the block address from control circuit 7, signal .PHI. generating circuit 10 maintains block select signal .PHI.L (or .PHI.R) for a selected array block at the "H" level, and sets block select signal .PHI.R (or .PHI.L) for a non-selected array block to the "L" level.
One word line decoder provided corresponding to an array block including a selected word line is activated among word line decoders 8 and 11. Here, assume that word line WLL included in array block MAL is selected. In this case, word line decoder 8 operates, decodes an internal address signal from control circuit 7, and transmits a word line drive signal at the internal high voltage Vpp level from Vpp generating circuit 5 onto word line WLL. As a result, access transistor 13 is turned on, and information stored in capacitor 12 is transmitted onto bit line BLL. Bit line /BLL maintains precharge level VH.
Then, sense amplifier drive signal .phi.p from sense amplifier drive signal generating circuit 6 is boosted to the internal power supply voltage Vcc1 level, and sense amplifier 21 is activated to differentially amplifying potentials on bit lines BLL and /BLL.
Then, column selecting operation (bit line pair selecting operation) is carried out according to an internal address signal generated by address signal Add strobed in response to the falling of column address strobe signal /CAS, writing/reading of data for memory cells (MC1) on a selected column is carried out. Whether data is written or read out is determined by signals /OE and /WE.
When writing/reading of data is complete, row address strobe signal /RAS is brought to a non-active state, and the signal potential on a selected word line WL4 attains the "L" level, followed by sense amplifier drive signal .phi.p attaining the "L" level.
Then, block select signal .PHI.R which was in a non-active state attains the "H" level, block select gates 22 and 23 are turned on, bit line equalize signal BLEQ attains the "H" level, and bit lines BLL, /BLL, BLR, and /BLR are precharged and equalized.
Block select signal .PHI.L or .PHI.R from signal .PHI. generating circuit 10 is at the internal high voltage Vpp level because of the following reason. During the restoring operation after completion of the sensing operation, sense amplifier 21 sets, according to storage data of memory cell MC1 (or MC2), corresponding bit lines BLL and /BLL (or BLR and /BLR) to the internal power supply voltage Vcc1 level and a ground potential Vss level. Between sense amplifier 21 and bit lines BLL and /BLL (or BLR and /BLR), block select gates 16 and 17 (or 22 and 23) are provided. Block select gates 16 and 17 (or 22 and 23) can transmit a voltage corresponding to a voltage applied to their gates minus the threshold voltage to corresponding bit lines BLL and /BLL (or BLR and /BLR). In order to eliminate the influence of loss of the threshold voltage in block select gates 16 and 17 (or 22 and 23), and to transmit a voltage at the internal power supply voltage Vcc1 level to bit lines BLL and /BLL (or BLR and /BLR), block select signal .PHI.L or .PHI.R is set at the internal high voltage Vpp level. Block select signal .PHI.L or .PHI.R may be set at the internal high voltage Vpp level only at the time of memory cycle, or only at the time when so-called "restoring operation" is carried out. Block select signal .PHI.L or .PHI.R has only to be at the internal high voltage Vpp level when a voltage at the internal power supply voltage Vcc1 level is transmitted to corresponding bit lines BLL and /BLL (or BLR and /BLR).
Word line decoders 8 and 11 generate a word line drive signal at the internal high voltage Vpp level because of the following reason. Memory cell MC1 (or MC2) writes storage data in memory cell capacitor 12 (or 14) through access transistor 13 (or 15). In order to sufficiently increase the amount of stored electric charge of capacitor 12 (or 14), it is necessary to transmit as high a voltage as possible to capacitor 12 (or 14) from bit line BLL (or BLR). In order to eliminate the influence of loss of the threshold voltage in access transistor 13 (or 15), and to transmit a voltage at the internal power supply voltage Vcc1 level to capacitor 12 (or 14), a word line drive signal at the internal high voltage Vpp level is used.
Intermediate voltage VH from Vcc/2 generating circuit 2 is applied to the cell plates of capacitors 12 and 14 because of the following reason. Ground voltage Vss or internal power supply voltage Vcc1 is applied to the opposing electrodes (storage nodes) of capacitors 12 and 14. From the standpoint of precise sensing operation (sensing margin), it is preferable that the amount of potential change of a bit line BL (which indicates BLL, /BLL, BLR, /BLR collectively) is made equal at the time of reading data of "H" at the Vcc1 level and at the time of reading data of "L" at the Vss level. Bit line BL is precharged to intermediate voltage VH. Therefore, in order to make the amount of potential change from the precharge level VH of bit line BL at the time of reading memory cell data equal between the time of reading data of "H" and at the time of reading data of "L", intermediate voltage VH is applied to the cell plates of capacitors 12 and 14. The amount of stored electric charge Q of the storage nodes of capacitors 12 and 14 at the time of storing data of "H" is C.multidot.Vcc1/2, and the amount of stored electric charge Q at the time of writing data of "L" is -C.multidot.Vcc1/2, wherein C is the capacitance of capacitors 12 and 14. More specifically, application of intermediate voltage VH to the cell plates of the memory cell capacitors makes the amount of potential change of bit line BL equal between the time of reading data of "H" and the time of reading data of "L".
The conventional DRAM down-converts external power supply voltage EXV using an internal Vcc generating circuit, generates internal power supply voltage Vcc1, and applies internal power supply voltage Vcc1 to each circuit, so that a signal amplitude is made small to reduce current consumption and power consumption.
In order to implement lower power consumption using lower operation power supply voltage, however, a signal at a required voltage level must be generated with as low power consumption as possible without the operation speed decreased by reduction of internal operation power supply voltage. Description will now be given of a circuit affected by reduction of internal power supply voltage Vcc1.
(i) Vbb generating circuit /Vpp generating circuit:
Negative voltage Vbb applied to the semiconductor substrate region as a bias voltage and internal high voltage Vpp used for driving a word line or the like are both generated using charge pump operation of a capacitor. A Vbb generating circuit will be described hereinafter.
FIG. 55 is a diagram showing one example of the structure of a Vbb generating circuit 3 shown in FIG. 54. Referring to FIG. 55, Vbb generating circuit 3 includes a pump drive signal generating circuit 224 providing a clock signal CK having a prescribed pulse width and a prescribed period, a pump circuit 225 generating negative voltage Vbb by charge pumping operation according to block signal CK from pump drive signal generating circuit 224, and a level detecting circuit 223 stopping generation of clock signal CK by pump drive signal generating circuit 224 when negative voltage Vbb generated by pump circuit 225 attains a prescribed level. Level detecting circuit 223, pump drive signal generating circuit 224, and pump circuit 225 receive internal power supply voltage Vcc1 as one operation power supply voltage and ground voltage Vss as the other power supply voltage.
Level detecting circuit 223 includes an n channel MOS transistor 87 having its source connected to an output node (or semiconductor substrate region) NA of pump circuit 225, and its gate and drain connected to a node NB, and an n channel MOS transistor 79 provided between node NB and a node NC and receiving ground voltage Vss at its gate, and a p channel MOS transistor 78 connected between an internal power supply node Vcc1 and node NC and receiving ground voltage Vcc at its gate. Note that power supply nodes and voltages applied thereto have the same reference characters in the following description.
MOS transistor 78 has large on resistance, and serves as a resistance element. MOS transistor 79 has small on resistance, and current supplying capability larger than that of MOS transistor 78. MOS transistor 79 is rendered conductive when the potential at node NB is Vss-Vthn or less, and sets node NC at the "L" level. Vthn is a threshold voltage of MOS transistor 79. MOS transistor 87 serves as a diode, and maintains a difference in potentials at node NB and node NA at the threshold voltage Vthn when rendered conductive.
Pump drive signal generating circuit 224 includes an inverter 91 inverting a signal at node NC of level detecting circuit 223, a 2-input NOR circuit 101 receiving an output signal from inverter 91 at one input, and three stages of cascade-connected inverters 92, 93, and 94 receiving an output signal from NOR circuit 101. NOR circuit 101 operates as an inverter when an output signal from inverter 91 is at the "L" level. In this state, NOR circuit 101, inverters 92 and 93 form a ring oscillator, and a clock signal having a prescribed pulse width and a prescribed period is generated. When an output signal from inverter 91 is at the "H" level, an output signal from NOR circuit 101 is fixed to the "L" level, clock signal CK is fixed to the "H" level, and pump drive signal generating circuit 224 stops generation of clock signal CK.
Pump circuit 225 includes an inverter 95 receiving clock signal CK from pump drive signal generating circuit 224, two stages of cascade-connected inverters 96 and 97 receiving an output signal from inverter 95, a capacitor 103 capacitively coupling an output portion of inverter 97 and a node N6, two stages of cascade-connected inverters 98 and 99 receiving an output signal from inverter 95, a capacitor 104 capacitively coupling an output portion of inverter 99 and a node N5, a capacitor 105 capacitively coupling an output portion of inverter 98 and a node N7, p channel MOS transistors 80 and 82 discharging the potentials at nodes N5 and N6 to the ground potential level in response to the potential at node N7, a p channel MOS transistor 83 clamping the potential on node N7 to the threshold voltage Vthp level, and a p channel MOS transistor 81 rendered conductive in response to the potential on node N6 for supplying a negative voltage from node N5 to output node NA. It should be noted that Vthp is the threshold voltage of p channel MOS transistors 80, 81, 82 and 83. Operation of pump circuit 225 will now be described with reference to FIG. 56.
In FIG. 56, a state is shown where pump circuit 225 conducts pumping operation stably. When clock signal CK rises to the "H" level, an output signal from inverter 98 also rises to the "H" level, and the potential on node N7 is increased by capacitive coupling (charge pump) of capacitor 105. Increase in the potential on node N7 brings MOS transistor 13 to an on state, and the potential on node N7 is clamped to .vertline.Vthp.vertline.. On the other hand, output signals from inverters 97 and 99 attain the "L" level, and the potentials on nodes N6 and N5 are decreased to negative potentials by capacitive coupling of capacitors 103 and 104. The potentials at nodes N6 and N5 are at the -Vcc1 level, as will be described later. MOS transistors 80 and 82 are turned off, because they receive the potential of .vertline.Vthp.vertline. at their gates. When the potential of negative voltage Vbb from output node NA is higher than -Vcc1+.vertline.Vthp.vertline., MOS transistor 81 is turned on, and there is a current flow to node N5 from node NA. More specifically, negative electric charge is supplied from node N5 to node NA. As a result, the potential at node NA is decreased.
When clock signal CK falls to the "L" level, an output signal from inverter 98 falls to the "L" level, and output signals from inverters 97 and 99 rise to the "H" level. The potential at node N5 attains the negative potential level (-Vcc1+.vertline.Vthp.vertline.) by capacitive coupling of capacitor 105. On the other hand, although the potentials at nodes N6 and N5 once increase by capacitive coupling of capacitors 103 and 105, the potentials are discharged to the ground potential Vss level because of an on state of MOS transistors 80 and 82. MOS transistor 81 is turned off because the potential at node NA is lower than the potentials at nodes N5 and N6. When output signals from inverters 95 and 99 fall to the "L" level, the potential at node N5 decreases to the voltage level of -Vcc1 and the potential at node N6 also decreases to the voltage level of -Vcc1 similarly. Therefore, MOS transistor 81 can transmit the potential of -Vcc1+.vertline.Vthp.vertline. to node NA. More specifically, negative voltage Vbb can decrease down to -Vcc1+.vertline.Vthp.vertline..
Although the negative voltage Vbb is applied to the semiconductor substrate region, the reverse bias voltage is applied to a PN junction formed between the semiconductor substrate region and an impurity region formed on the surface thereof. Therefore, from the standpoint of breakdown voltage of the PN junction, the value of negative voltage Vbb is preferably small. Making the value of negative voltage Vbb larger than necessary (more negative) is not preferable from the standpoint of current consumption. Therefore, level detecting circuit 223 detects the voltage level of negative voltage Vbb provided from node NA, and stops generation of clock signal CK by pump drive signal generating circuit 224 when negative voltage Vbb is -2.multidot.Vthn or less. More specifically, in level detecting circuit 223, when negative voltage Vbb is -2.multidot.Vthn or less, the potential at node NB is -Vthn or less, MOS transistor 79 receiving ground voltage Vss at its gate is turned on, and the potential at node NC is decreased to the "L" level. As a result, an output from inverter 91 attains the "H" level, an output from NOR circuit 101 is fixed to the "L" level, and clock signal CK is fixed to the "H" level in pump drive signal generating circuit 224. Pump operation of pump circuit 225 is halted, and supply of negative electric charge (electrons) to node NA is stopped.
Pump circuit 225 causes negative electric charge (electrons) to flow out to output node NA for every one cycle of clock signal CK. The speed at which negative voltage Vbb from node NA decreases is determined by the amount of current (the amount of negative electric charge) supplied from MOS transistor 81 of the output portion of pump circuit 225. As shown in FIG. 57, the potential at node N5 basically vibrates between Vss and -Vcc1. MOS transistor 81 supplies negative electric charge to node NA according to a difference in potentials between nodes N5 and NA. As shown by hatching in FIG. 57, negative electric charge is supplied for every one cycle. However, the amount of negative electric charge supplied from output node NA is decreased as the potential level of negative voltage Vbb decreases. When supply of negative electric charge by MOS transistor 81 is stopped, Vbb=V(N5)+.vertline.Vthp.vertline., wherein V(N5) is the potential at node N5.
Therefore, as the potential level of negative potential Vbb approaches -Vcc1+.vertline.Vthp.vertline., negative voltage current (the amount of negative electric charge) flowing through MOS transistor 81 decreases, and the speed at which the potential decreases is decreased. When internal power supply voltage Vcc1 is decreased for low power consumption, the threshold voltage Vthn of the MOS transistor is not scaled down (because of larger subthreshold current). Therefore, the potential level of the lowest potential -Vcc1 which node N5 attains approaches a target voltage level -2.multidot.Vthn of negative voltage Vbb. Accordingly, the speed at which the potential of negative voltage Vbb decreases is decreased (because of reduction of the amount of supply of negative electric charge), and long time is required for negative voltage Vbb to attain a prescribed level -2.multidot.Vthn.
Further, when a substrate bias voltage (negative voltage Vbb) varies due to substrate current at the time of operation of the semiconductor substrate, the substrate bias voltage cannot be returned to a prescribed potential level -2.multidot.Vthn at a high speed because of decrease of the amount of supply of negative electric charge from pump circuit 225. As a result, stable operation cannot be guaranteed.
The above problem of reduction of efficiency of the negative voltage Vbb generating circuit caused by low power supply voltage arises in the Vpp generating circuit generating internal high voltage Vpp, similarly. In the internal high voltage generating circuit (Vpp generating circuit), by replacing the p channel MOS transistors of pump circuit 225 shown in FIG. 55 with n channel MOS transistors, and by replacing ground voltage Vss with internal power supply voltage Vcc1, a pump circuit for generating internal high voltage Vpp is obtained theoretically. A level sensing circuit for internal high voltage Vpp is also implemented by replacing negative voltage Vbb in the level sensing circuit shown in FIG. 55 with internal high voltage Vpp, reversing conductivity types of the MOS transistors, and by replacing ground voltage Vss with internal power supply voltage Vcc1.
As described above, when a pump circuit is used as a conventional negative voltage generating circuit and a conventional internal high voltage generating circuit, and the internal power supply voltage level is further decreased for low power consumption, electric charge cannot be supplied efficiently, and a voltage at a prescribed level (negative voltage Vbb and internal high voltage Vpp) cannot be generated at a high speed. Accordingly, a semiconductor memory device which operates stably with lower power consumption cannot be implemented.
(ii) BLEQ generating circuit
FIG. 58 is a diagram showing schematically the structure of BLEQ generating circuit 9 shown in FIG. 54. Referring to FIG. 58, BLEQ generating circuit 9 generates bit line equalize signal BLEQ in response to an internal row address strobe signal RAS applied from control circuit 7 shown in FIG. 54. BLEQ generating circuit 9 operates with internal power supply voltage Vcc1 and ground voltage Vss as operation power supply voltages. Internal row address strobe signal RAS is generated from control circuit 7 shown in FIG. 54 in response to external row address strobe signal /RAS. When internal row address strobe signal RAS is at the "H" level, bit line equalize/precharge signal BLEQ attains the "L" level. Description will be given hereinafter of operation of BLEQ generating circuit 9 shown in FIG. 58 with reference to FIG. 59 which shows the operation waveform diagram.
When external row address strobe signal /RAS is at the "H" level, internal row address strobe signal RAS is at the "L" level, and bit line equalize signal BLEQ from BLEQ generating circuit 9 is at the "H" level of the internal power supply voltage Vcc1 level. As a result, MOS transistors 18, 19, and 20 are turned on, precharging and equalizing bit lines BL and /BL (which indicate bit lines BLL, /BLL, and BLR, /BLR shown in FIG. 54 collectively) to a prescribed intermediate voltage VH.
When external row address strobe signal /RAS falls to the "L" level, internal row address strobe signal /RAS accordingly rises to the "H" level, and a memory cycle starts. In response to the rising of internal row address strobe signal RAS, bit line equalize signal BLEQ from BLEQ generating circuit 9 attains the "L" level, MOS transistors 18, 19, and 20 are turned off, and bit lines BL and /BL are brought to a floating state at intermediate voltage VH.
Then, a word line, not shown, is selected, and the potential increases. Data of memory cells connected to the selected word line is transmitted to bit line BL or /BL. Then, sensing operation is carried out. The potentials on bit lines BL and /BL attain "H" at the internal power supply voltage Vcc1 level and "L" at the ground voltage Vss level depending on data read out from memory cells.
When the memory cycle is complete, external row address strobe signal /RAS rises to the "H" level. After a prescribed time, internal row address strobe signal /RAS falls to the "L" level. In response to the falling of internal row address strobe signal RAS, bit line equalize signal BLEQ from BLEQ generating circuit 9 rises to the "H level, and MOS transistors 18, 19, and 20 are turned on. This causes bit lines BL and /BL to be precharged/equalized to the internal voltage VH level again.
Bit line equalize signal BLEQ is at the internal power supply voltage Vcc1 level. When the voltage level of internal power supply voltage Vcc1 is decreased for low power consumption of a semiconductor memory device, the potential at the "H" level of bit line equalize signal BLEQ decreases accordingly. In this case, the gate-source voltages of MOS transistors 18-20 become small (the sources of n channel MOS transistors are electrodes having a low potential), and their conductivities become small. Therefore, current supplying capabilities of MOS transistors 18-20 become small, and the potentials of bit lines BL and /BL are set at a prescribed intermediate voltage VH later as shown by a broken line in FIG. 59 after completion of the memory cycle. On the other hand, for external row address strobe signal /RAS, RAS precharge time tPR is set. Once it attains the "H" level, external row address strobe signal /RAS can be set to the "L" level again only after a lapse of RAS precharge time tPR (for reliably precharging an internal signal line to a prescribed potential). If the potentials of bit lines BL and /BL cannot be precharged/equalized to a prescribed intermediate voltage VH within a prescribed time, the RAS precharge time becomes longer, and it takes longer time to start the next memory cycle. Accordingly, the semiconductor memory device cannot be accessed at a high speed.
(iii) Vcc/2 generating circuit
FIG. 60 is a diagram showing the structure of a conventional Vcc/2 generating circuit, which is found in pages 17 and 18 of Digest of Technical Papers, 1990 Symposium on VLSI Circuits, for example.
Referring to FIG. 60, the Vcc/2 generating circuit includes resistors 34 and 35 connected in series between power supply node Vcc1 and a ground node Vss, a resistor 36 connected between power supply node Vcc1 and a node ND2, an n channel MOS transistor 38 having its gate and drain connected to node ND2 and its source connected to a node ND1, a p channel MOS transistor 40 having its gate and drain connected to a node ND3 and its source connected to node ND1, a resistor 37 connected between node ND3 and ground node Vss, an n channel MOS transistor 39 connected between power supply node Vcc1 and node ND1 and receiving the signal potential at node ND2 at its gate, and a p channel MOS transistor 41 connected between node ND1 and ground node Vss and receiving the signal potential at node ND3 at its gate.
Resistors 34 and 35 have the same resistance value, and resistors 36 and 37 have a sufficiently large resistance value. Transistors 38 and 40 have respective threshold voltages Vthn and Vthp. Operation will now be described briefly.
Since resistors 34 and 35 have the same resistance value, the potential of node ND1 is Vcc1/2. Since resistors 36 and 37 have a sufficiently large resistance value, there is only a small current flow through MOS transistors 38 and 40. Therefore, MOS transistors 38 and 40 operate in a diode mode, the potential of node ND2 is Vcc1/2+Vthn, and the potential of node ND3 is Vcc1/2-.vertline.Vthp.vertline.. MOS transistors 39 and 41 have threshold voltages Vthn and Vthp, respectively. When the potential VH of node ND4 is lower than Vcc1/2, MOS transistor 39 is turned on, and MOS transistor 41 is turned off. Node ND4 is supplied with current from power supply node Vcc1 through MOS transistor 39, increasing voltage VH.
When voltage VH of node ND4 is higher than Vcc1/2, MOS transistor 39 is turned off, and MOS transistor 41 is turned on. Node ND4 is discharged through MOS transistor 41, decreasing the potential. As a result, voltage VH of node ND4 is set to intermediate voltage Vcc1/2.
MOS transistor 38 causes voltage drop between node ND2 and node ND1, and MOS transistor 40 causes voltage drop of .vertline.Vthp.vertline. between node ND1 and node ND3. Therefore, in order for Vcc1/2 generating circuit 2 to operate, the condition of Vcc1.gtoreq.Vthn+.vertline.Vthp.vertline. must be satisfied. More specifically, internal power supply voltage Vcc1 has a lower limit value, and low power consumption cannot be implemented by reduction of the internal power supply voltage.
Further, there is also a problem that current consumption is increased depending on a defective mode of a memory cell as described below.
As shown in FIG. 61, consider the case where short-circuiting occurs between the electrode (cell plate) of a memory cell capacitor MQ and a word line WL. Intermediate voltage VH from Vcc/2 generating circuit 2 is applied to the electrode of memory cell capacitor MQ. Therefore, when the potential of word line WL is at the "L" level, there is a current flow from power supply node Vcc1 through MOS transistor 39 shown in FIG. 60 to word line WL through node ND4 and the memory cell capacitor electrode (cell plate). In general, in order to ensure the production yield, a DRAM is used as a non-defective product even if there is a leakage current of 0.2 mA in memory cell capacitor MQ, provided that a defective memory cell in which the capacitor electrode is short-circuited is replaced with a redundancy circuit (the defective memory cell per se exists in the device). Since current must be supplied to the capacitor electrode of the defective memory cell through the Vcc/2 generating circuit, the internal power supply voltage generating circuit must have current supplying capability of 0.2 mA even at the time of stand-by of the DRAM. Accordingly, the stand-by current of the DRAM cannot be made small.
In addition, even when voltage VH from node ND4 attains a prescribed level Vcc1/2, current is consumed wastefully, because the gate-source voltages of MOS transistors 39 and 41 are Vthn and Vthp, respectively, and there is a subthreshold current flow in ground node Vss from power supply node Vcc1 through MOS transistors 39 and 41. In order to reduce the subthreshold current, ions must be implanted into the channel regions of transistors 39 and 41, and the threshold voltages Vthn and .vertline.Vthp.vertline. of MOS transistors 39 and 41 must be increased. In this case, an additional manufacturing step for adjusting the threshold voltages of MOS transistors 39 and 41 is required, preventing simplification of the manufacturing process. When the threshold voltages of MOS transistors 39 and 41 are increased, even if voltage VH from node ND4 is offset from a prescribed intermediate voltage Vcc1/2, MOS transistors 39 and 41 are not turned on. A non-sensitive belt where the Vcc/2 generating circuit does not operate even if voltage VH changes from a prescribed level, making it impossible to precisely maintain voltage VH at the intermediate voltage level.
(iv) Internal power supply voltage generating circuit
FIG. 62 is a diagram showing the structure of a conventional internal power supply voltage generating circuit. Referring to FIG. 62, conventional internal power supply voltage generating circuit 4 includes an activation internal power supply voltage generating circuit 313 operating at the time of activation (during memory cycle) and supplying internal power supply voltage Vcc1, and a stand-by internal power supply voltage generating circuit 314 maintaining internal power supply voltage Vcc1 at a prescribed voltage level at the time of stand-by.
Activation internal power supply voltage generating circuit 313 includes an inverter 170 inverting row address strobe signal /RAS (generated from control circuit 7 shown in FIG. 54), a p channel MOS transistor 310 rendered conductive in response to an output signal from inverter 170 for transmitting external power supply voltage EXV to a node ND5, an N channel MOS transistor 164 provided between node ND5 and a node ND7 for receiving a reference voltage Vref at its gate, an n channel MOS transistor 165 provided between a node ND6 and node ND7 for receiving the signal potential on a node ND9 at its gate, an n channel MOS transistor 166 provided between node ND7 and ground node Vss for receiving an output from inverter 170 at its gate, a p channel MOS transistor 158 provided between node ND5 and an external power supply node EXV receiving external power supply voltage EXV, and a p channel MOS transistor 159 provided between external power supply node EXV and node ND6. Node ND6 is connected to respective gates of MOS transistors 158 and 159. MOS transistors 158 and 159 form a current mirror circuit, and MOS transistors 164 and 165 form a source coupling type comparing circuit.
Stand-by internal power supply voltage generating circuit 314 includes an n channel MOS transistor 167 provided between a node ND10 and a node ND12 for receiving reference voltage Vref at its gate, an n channel MOS transistor 168 provided between a node ND11 and node ND12 for receiving the signal potential on a node ND9 at its gate, a p channel MOS transistor 161 provided between external power supply node EXV and node ND10, and a p channel MOS transistor 162 provided between node ND11 and external power supply node EXV. Node ND11 is connected to respective gates of MOS transistors 161 and 162. MOS transistors 161 and 162 form a current mirror circuit, and MOS transistors 167 and 168 form a source coupling type comparing circuit. Stand-by internal power supply voltage generating circuit 314 further includes an n channel MOS transistor 159 provided between node ND12 and ground node Vss for receiving internal power supply voltage Vcc1 at its gate to serve as a constant current source.
Internal power supply voltage generating circuit 4 further includes a p channel MOS transistor 160 rendered conductive in response to the signal potential on node ND5 of activation internal power supply voltage generating circuit 313 for supplying current to a node ND8 from external power supply node EXV, a p channel MOS transistor 163 rendered conductive in response to the signal potential on node ND10 of stand-by internal power supply voltage generating circuit 314 for supplying current from external power supply node EXV to output node ND8, and resistors 171 and 172 connected in series between node ND8 and ground node Vss. The resistance values of resistors 171 and 172 are so set that the ratio is 2:3, for example. Operation will now be described briefly.
In a stand-by state, row address strobe signal /RAS is at the "H" level, and an output from inverter 170 is at the "L" level. In this state, MOS trnsistor 310 is turned on, and MOS transistor 166 is turned off. Node ND5 is charged to external power supply voltage EXV by MOS transistor 310, and MOS transistor 160 is turned off.
On the other hand, in stand-by internal power supply voltage generating circuit 314, MOS transistor 169 operates as a constant current source, and compares reference voltage Vref and the signal potential on node ND9. When the signal potential on node ND9 is higher than reference voltage Vref, the potential of node ND10 increases, thereby decreasing the conductance of MOS transistor 163. On the other hand, when the signal potential on node ND9 is lower than reference voltage Vref, the potential of node ND10 decreases, thereby increasing the conductance of MOS transistor 163, and supplying current to node ND8. This makes the signal potential on node ND9 equal to reference voltage Vref. The ratio of the resistance values of resistors 171 and 172 are set to 2:3. Therefore, internal power supply voltage Vcc1 is maintained at a voltage level of 5.multidot.Vref/3. When the value of reference voltage Vref is 1.5 V, for example, the value of internal power supply voltage Vcc1 is maintained at 2.5 V.
When an active cycle (memory cycle) starts, row address strobe signal /RAS attains the "L" level, and activation internal power supply voltage generating circuit 313 is brought to an active state. More specifically, an output signal from inverter 170 attains the "H" level, MOS transistor 310 is turned off, and MOS transistor 166 is turned on. Operation of a current mirror type differentially amplifying circuit formed of MOS transistors 158, 159, 164, and 165 is the same as that of the stand-by internal power supply voltage generating circuit. By adjusting the conductance of MOS transistor 160 according to the relationship between the voltage of node ND9 and reference voltage Vref, internal power supply voltage Vcc1 on node ND8 is maintained at a constant voltage level of 5.multidot.Vref/3.
At the time of stand-by when internal power supply voltage Vcc1 is hardly used, current consumption at the time of stand-by is reduced by operating only stand-by internal power supply voltage generating circuit 314 consuming a little current. In the memory cycle (active cycle) when internal power supply voltage Vcc1 is consumed (current is consumed from internal power supply voltage Vcc1 by charging of a signal line by operation of internal circuits), a large amount of current is supplied to node ND8 by MOS transistor 10 having a large current drivability, thereby stabilizing internal power supply voltage Vcc1.
With the structure of the conventional internal power supply voltage generating circuit shown in FIG. 62, however, there is always a current flow from node ND8 to ground node Vss through resistors 171 and 172. When the resistance values of resistors 171 and 172 are increased in order to decrease a current flow through resistors 171 and 172, RC delay from node ND8 to node ND9 becomes larger. In this case, change of the signal potential on node ND8 is transmitted to circuits 313 and 314 later. Change of internal power supply voltage Vcc1 cannot be followed at a high speed, and internal power supply voltage Vcc1 cannot be kept at a constant level stably.
More specifically, with the structure of the conventional internal power supply voltage generating circuit, operating the semiconductor memory device with low power consumption prevents stable generation of internal power supply voltage.
As described above, with the structure of the conventional semiconductor memory device, low power consumption cannot be implemented without decreasing performance.